Embodiments relate generally to cache tracking, and more specifically, to cache line history tracking using an instruction address register file.
One of the goals of a microprocessor is to achieve high performance. High performance can be measured by how many instructions are completed per unit of time, such as a clock cycle. The more quickly instructions complete, the better the performance of a microprocessor.
There are, however, inherent hazards that occur when a processor executes a program. The program may encounter a branch instruction that redirects program flow to a different part of the program, causing the processor to redirect and start fetching from the new instruction stream. That new instruction stream may not be in the L1 cache, and therefore not readily available to deliver instructions to the processor. Events such as unexpected branches, incorrectly predicted branch directions and cache misses result in lower processor performance since they delay instruction completion.
Programmers may have some insight into how the instructions of their programs will execute on a microprocessor. Usually the only evidence that can be observed is the direct output of the program. Tools and methods have been developed to provide evidence such as instruction counts and branch history information. Programmers can view instrumentation information from program execution to determine, for example, how often instructions complete. A large gap between instructions completing may be indicative of a cache miss at that point in the program. Closing these gaps is an opportunity to achieve better processor performance. By seeing where program inefficiencies exist from instrumentation data, programmers can employ methods to alleviate such performance problems.